This invention relates to a method of manufacturing a semiconductor device such as a GaAs-FET (field effect transistor).
In order to enhance the performances of a GaAs-FET (field effect transistor) and an IC (integrated circuit), fabrication technology for submicron regions is needed. To this end, fine processing techniques based on the electron-beam lithography have been studied. In the current situation, however, there is the disadvantage that the through-put cannot be raised. Although it has been attempted to enhance the processing accuracy by resorting to the conventional photolithography and utilizing self-alignment, the prior-art methods have the disadvantages of inferior tolerance of heating and small processing margin.
FIG. 1 is a sectional view showing the fundamental setup of a GaAs-FET. Referring to the figure, numeral 1 designates a GaAs substrate, numeral 2 a source region, numeral 3 a drain region, numeral 4 a gate region which is formed between the source region 2 and the drain region 3, numerals 5, 6 and 7 a source electrode, drain electrode and gate electrode, respectively, and numeral 8 a protective film.
In such GaAs-FET, it is necessary for enhancing the performance of the device to narrow the interval between the source region 2 and the drain region 3 to the utmost. In addition, the gate electrode 7 must be fined so as to reduce the capacitance of the gate electrode 7. With the fabrication technology based on the conventional photolithography, the wavelength limitation of light makes it impossible to fabricate patterns of or below 1 .mu.m reliably and difficult to attain a superposition accuracy within .+-.1 .mu.m, so that a satisfactory performance cannot be achieved.
Examples of such GaAs-FET are found in ISSCC Dig. of Tech. Papers, p. 218 (1981) by N. Yokoyama et al, etc.